Nand 4011 design
Hi, im Perlis polytechnic student, and now i undergo last semester already. And i taken one interesting subject is CMOS IC design. So this is one of lab work that i uploading. Using L-Edit to design NAND gate.
Published on: Mar 3, 2016
Transcripts - Nand 4011 design
[CMOS DESIGN] March 8, 2013DECEMBER 2012 SESSION Page 1ELECTRICAL ENGINEERING DEPARTMENTEE603-CMOS INTEGRATED CIRCUIT DESIGNLAB REPORT 3Designing Basic Logic Gates and ICNo Registration No. Name1. 18DTK10F1036 CHONG WEI TING2. 18DTK10F1034 ADLAN BIN ABDULLAHCLASS : DTK 6BLECTURER : EN. MUHAMAD REDUAN BIN ABU BAKARDATE SUBMITTED : 8th MARCH 2013(Date submitted is one week after date lab)TUANKU SYEDSIRAJUDDINPOLYTECHNICMARKSLab Work :Lab Report:Total :
[CMOS DESIGN] March 8, 2013DECEMBER 2012 SESSION Page 2LAB 3 : DESIGNING BASIC LOGIC GATES & ICAim: Designing NAND gates, then make a cell of IC 4011 using L-edit software.Objective:After students had done this laboratory, then students should be able to:1) Introduce schematic circuit, logic symbols and truth table of NAND gates.2) Design individual 2-input logic gates (NAND).3) Design IC4011 (2-input NAND gate).Apparatus: PC-set & L-edit student V 7.12 software.This is an AND gate with the output inverted, as shown by the o on the output.The output is true if input A AND input B are NOT both true: Q = NOT (A AND B)A NAND gate can have two or more inputs, its output is true if NOT all inputs are true.Figures: a) Logic Symbol; b) static schematic symbol; and c) truth table of NANDINTRODUCTIONa) b) c)
[CMOS DESIGN] March 8, 2013DECEMBER 2012 SESSION Page 3Draw the CMOS static logic diagram and stick diagram ofthe NAND gate.NOTESMetal 1Metal 2PolyP- diffusionn-diffusioncontact
[CMOS DESIGN] March 8, 2013DECEMBER 2012 SESSION Page 41. DESIGN INDIVIDUAL NAND GATESa) Procedure for create new file similar to the previous lab.b) Combined the both of PMOS in parallel and both of NMOS in series to build aNAND gates, and then selected the metal2 and drawn overlap to the metal1, wehad done a complete single NAND layout. And label it to identify connection. Wehad to follow the properly design rule to avoid the error occurrence.LAB WORKACTIVITY
[CMOS DESIGN] March 8, 2013DECEMBER 2012 SESSION Page 5c) Selected ToolDRC, to ensure that the design does not violating any designrules.d) Specify the size and area of NAND logic gates.Area: 42µm X 35µm=1470
[CMOS DESIGN] March 8, 2013DECEMBER 2012 SESSION Page 6PART 2: DESIGN NAND GATES IC (4011)a) Selected an individual NAND gates layout, and pressed ctrl+Cctrl+V, and thendrag and moved the copy of second NAND gate to the same position with thefirst NAND GATES.b) Used same method of previous step to build two more NAND gate layout copy,and then kept the properly arrangement to their own position and madeconnection to the metal 2 with each edge of gate. (Always adjust the suitablelength of metal 2, and also always refer design rule for entire layout)
[CMOS DESIGN] March 8, 2013DECEMBER 2012 SESSION Page 7c) Selected ToolDRC, to ensure that the design does not violating any designrules.d) Selected the cellNew, to open the new file. Typing the New Cell Name into textbox, then press OK. The new window would appear.
[CMOS DESIGN] March 8, 2013DECEMBER 2012 SESSION Page 8e) Selected CellInstance, and then press “OK” to create a cell of the previouslayout.f) New cell had been created, and then we had to label of the pin name surroundedge of the NAND cell.
[CMOS DESIGN] March 8, 2013DECEMBER 2012 SESSION Page 9Area: 98µm X 90µm=88204 NAND GATE IC 4011
[CMOS DESIGN] March 8, 2013DECEMBER 2012 SESSION Page 10This lab work will consider the complete NAND gates layout that based on IC 4011Cell that involve four NAND gates is presented, which after completing the lab phase,we will be able to design an individual 2-input logic gates which is NAND gate based ongiven specification design rule.Before start the design of CMOS layout, we able to recognize schematic circuit,logic symbols and truth table of NAND gates. In the design process, we will know howto avoid the CMOS phenomenon such as parasitic for every individual gate, so one ofthe typical solution is place substrate tap and well tap as body tap for pull down networkand pull up network/. After an individual NAND gate design, we had able to check theirdesign rule without any design error, else fix the error well. Finally, we able to instancesthe combination of four NAND layout of a small IC block, which is 4011.CONCLUSION