NARTHANAA KRISHNAN Address : 718 University Ave SE, Apt 4, Minneapolis MN- 55414
Email : Mobile : +1-612-...
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Published on: Mar 3, 2016

Transcripts - NarthanaaK_Resume

  • 1. NARTHANAA KRISHNAN Address : 718 University Ave SE, Apt 4, Minneapolis MN- 55414 Email : Mobile : +1-612-702-1183 OBJECTIVE: Actively looking for internship/co-op opportunities in VLSI design that utilizes my technical and academic skill-set. EDUCATION: Master of Science in Engineering (Electrical Engineering – VLSI) Fall’15-May’17(Expected) University of Minnesota, Twin Cities GPA 3.5/4 Relevant courses: VLSI Design, Advanced VLSI Design, Front-end VLSI design lab, Advanced Computer Architecture, Advanced VLSI Verification Bachelor of Technology (Electronics & Communication Engineering) Aug’11-May’15 Amrita University, Coimbatore, India GPA 9.4/10 Relevant courses: VLSI System Design, VLSI Testing, Analog IC Design, Basic Analog Electronics, Advanced Analog Electronics, Digital Electronics, RF Circuit design, Digital Signal Processing, Microprocessors and Controllers WORK EXPERIENCE: Intern-Bachelors, Honeywell Technology Solutions Pvt Ltd, Madurai, India. Jan’15-Jun‘15  Developed an integrated IoT based emergency alerting system by building a generic rules processor in Arduino using C++ and a handheld user interface using Android Studio for the tools and development team RISE LABS- Indian Institute of Technology, Madras, India (Guide: Dr. V Kamakoti) Dec’13, Jun’14-Jul’14  Developed an Instruction Set Simulator for the ISA of IIT-M’s processor using C code. The speed of simulation was accelerat- ed by portioning IMEM based on the frequency of the instruction. Python script was developed to automate the verification  Implemented AMBA (3.0) BUS protocols- AHB, APB, Interconnecting Bridge in Bluespec SystemVerilog for IITM's processor PROJECTS: BACK-END VLSI PROJECTS: Design of 128kb SRAM sub-array (Guide: Dr. Chris Kim) Jan’16-Present  Full schematic and layout design of 1 GHz , 128kb SRAM with power gating and read/write assist circuitry in Cadence Virtu- oso under 45nm process, 80°C, 1.1V. Size transistors to meet SNM specifications (determined by Monte Carlo simulations) ASIC Design of 16-bit Ladner Fischer Tree Adder (Guide: Dr. Chris Kim) Oct’15-Dec’15  Full schematic and layout designed in Cadence Virtuoso achieving a post layout frequency of 954MHz, area 184µm2 and max. power of 685µW at 110°C, 1.1V, 45nm process. Grid based layout technique was adopted . Sized the tree stages to reduce worst case path delay and to optimize the EDP. With Vdd 0.7V, frequency was 387MHz, power 228.7 µW Design and analysis of 7-stage ring Oscillator (Guide: Dr. Chris Kim) Sep’15  Designed a fan-out 4, 7 stage ring oscillator using Cadence Virtuoso under 45nm process, 1.1V and 110°C. Achieved post- layout frequency of 1.3GHz. Analyzed performance tradeoffs for various PVT. Sized the transistors for minimum delay FRONT-END VLSI PROJECTS (RTL, Validation and Computer Architecture): Design of 4 way set associative cache memory controller (Guide: Dr. Gerald Sobelman) Jan’16-Present  Design the RTL of a 4-way, 16k set associative cache and its controller using Verilog. Generate ATPG and perform fault coverage. Extract gate level netlist using Synopsys Design Compiler and feed it to ICC to perform Physical Design. UVM based verification of 32-bits MIPS ALU (Guide: Dr. Gerald Sobelman) Oct’15-Dec’15  UVM based System Verilog Testbench including random, constraint random and directed test cases created to verify func- tioning of MIPS ALU under all combinations of input operands, instructions and control signals. Achieved 100% coverage Evaluating Adaptive Insertion Policy to achieve high performance caching (Guide: Dr. Ulya Karpuzku) Oct’15-Dec’15  Implemented MRU, Bimodal and Adaptive insertion policies for L2 cache on pipelined single core Alpha processor using SimpleScalar. Saw up to 54% reduction in MPKI over LRU. Analyzed dynamic/static power consumptions and performance tradeoffs for these policies across 90nm, 60nm 45nm and 32nm technologies using CACTI String Comparison Architecture for Network Intrusion Detection System (Guide: Dr. D S Harish Ram) Jul’14-Dec’14  Evaluated high performance string matching algorithms and designed a low latency architecture for their RTL implementa- tion in Xilinx-Spartan 6 FPGA using Verilog targeting high speed Network Intrusion Detection Systems for gigabit Ethernet RESEARCH PUBLICATIONS ( Multiple gate devices – DG FET and FinFET): Sushmitha A.; Narthanaa K.;Aravindan, I; A.S.Ajay; Sundari, B Bala Tripura, “Towards MUGFETs: A power Reduction Perspective,” International Conference on Green Computing Communication and Electrical Engineering (ICGCCEE),2014,vol., no., 1,6, 6-8 March 2014 TECHNICAL SKILLS: Simulation/Design tools : Cadence virtuoso (Schematic and Layout), Calibre (DRC, LVS, PEX), Spice, Cosmoscope, Synopsys VCS (with DVE), Design Compiler and ICC, SimpleScalar, Cacti, MATLAB, ModelSim Scripting /Programming Languages : PERL, Python, C, C++ Hardware Description Languages : Verilog, SystemVerilog, Bluespec SystemVerilog, VHDL

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