Naresh Bollam Contact: +91-9423592338
I worked at client PMC-Sierra, Bangalore...
Project 2 internship trainee (ATPG pattern generation & block level simulation)
Duration 2 Months
Description Objective: T...
of 2


Published on: Mar 3, 2016

Transcripts - NARESH BOLLAM

  • 1. Naresh Bollam Contact: +91-9423592338 EXPERIENCE & GOALS I worked at client PMC-Sierra, Bangalore in April-2015 to Oct-2015 with total experience of +0.6 yr (2 months internship trainee in DFT & 4+ months in the DFT live project). I have the ability to work effectively in a team and want to acquire knowledge, skills and experience with the best in semiconductor industry. Want to be updated with the latest trends in semiconductor technology and strive to grow through excellence in execution of work. TECHNICAL SKILLS EDA Tools Cadence(EDI,Virtuoso,NCSim), Xilinx ISE, QuestaSim, ModelSim, Quartus II, Hardware Description Languages Verilog Programming Languages C, C++(basics), Matlab Scripting Language TCL(basics), Shell scripting, Perl EDUCATION Degree and Date Institute Specialization (Score) M.Tech. VIT University, Chennai. VLSI Design (7.96) B.E , JUNE – 2010 WIT College, Solapur Electronics Engg (72 %) Diploma-2007 Government polytechnic, Solapur (MH) Electrical Engg (76.15%) X (SSC) -2003 N. B. Banda Prashala Solapur (MH) (70.93%) EXPERIENCE At client PMC-Sierra DFT Engineer (Back End) Projects: Project 1 LUXOR_HD(In internship) Duration 4+months ( June2015 to till) Description ATPG pattern generation,BIST,Simulation,Top-Mapping,Micro-mapping. Achievements:  Created ATPG setup in Encouter & Simulation setup for 28nm TSMC lib.  Given issue fixes.  Got to know about different block & different level issues.  Create BIST setup & Simulation in NCSim  Working on ATPG of 7 blocks.  Created setup for Top-mapping simulation in NCSim.  Created setup for Micro-mapping  Working on Pre-layout & Post-layout timing simulation and ATPG pattern generation.  Created setup for Ex-test and findout out emulated IC test coverage  Improved coverage analysis for below 99% coverage blocks.  Able to debug the simulation issues and resolved.  Able to handle 24 blocks for top-mapping simulation. This work started as support to the design team working on the project. The project is in end of coming phase, and the final deliverable phase is about to start. My work is mainly focused on to find out major issues that may cause timing simulation changes in later stages of the design. To be maintained each block coverage should be above 99 %.
  • 2. Project 2 internship trainee (ATPG pattern generation & block level simulation) Duration 2 Months Description Objective: This training was mainly focused on how to generate ATPG patterns and simulation Aim: Generation of generation of ATPG pattern, to debug simulation issues and to focus on coverage analysis. To trace broken chains in Cadence GUI and resolved the issues. Achievements:  Got to know about hierarchical Bottom-Up design approach & implementation.  The project involved extensive scripting with TCL hence got to know about how to automate the design flow.  Got the overview about full chip integration. Project 3 A CMOS Analog Front-end & Back-end Design for a MEMS Based Temperature Sensor Duration 8 Months Description Objective: The project addresses to the problem faced by how to generate a particular frequency range to a desired Temperature. The circuit consists of various building blocks that include PTAT current generator, current starved VCO, frequency t o current convertor, current subtractor and Integrator. Domain : MEMS and Analog IC design Achievements:  Successfully implemented integrated all sub circuits in a single module  Able to generate the frequency with respect to temperature variables  Got to know about , how to change the transistor width and height so, transistor comes into a saturation region. STRENGTHS  Can work effectively in a team , as well as individually  Mental toughness and self confidence.  Like to take challenges.  Good in self learning & exploring beyond boundaries. PUBLICATIONs Bollam Naresh Sudarshan, A. Ravi Sankar, "A CMOS Analog Front-End Circuit for a MEMS Based Temperature Sensor",International Journal of Research in Electronics & Communication Technology Volume 1, Issue 2, October- December,2013, pp. 01-06, © IASTER 2013, ISSN Online: 2347-6109, Print: 2348-0017 PERSONAL DETAILS Full Name: Naresh Sudarshan Bollam DoB: 23rd Dec Current Address: 205, Hampton Court, Outer Ring Road, Bellandur, Bangalore 560103. Permanent Address: 18/79, Madhav nagar, M.I.D.C. road,Solapur-413006.. Contact: 09423592338, 08007542923

Related Documents