NANDEESH THIMMAPPAPh:214-673-3599 2400 WaterviewParkway # 931 Richardson Texas -75080 nandeesh.thimmapp...
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Nandeesh Thimmappa Resume

Published on: Mar 3, 2016
Published in: Education      

Transcripts - Nandeesh Thimmappa Resume

  • 1. NANDEESH THIMMAPPAPh:214-673-3599 2400 WaterviewParkway # 931 Richardson Texas -75080 nandeesh.thimmappa@gmail.comProfileLooking for an entry level position in the field of IC Design and Verification for Fall 2013.  Adequate knowledge in digital design flow from architecture level to physical implementation. Hands-on experience in RTL coding, standard cell library generation, manual place and route and timing analysis.  Strong knowledge and experience on DFT techniques- ATPG/Scan, BIST with good debugging skills.  Proficient in C/C++ programming, Perl and Unix Shell Scripting .EducationM.S in Electrical Engineering, University Of Texas at Dallas 3.72/4 Aug 2013B.E in Electronics and Communication, Visvesvaraya Technological University 3.80/4 May 2010Certification : C, C++ under "Infosys Campus Connect ".Work Experience :Co-op Intern in DFX Verification Team, Advanced Micro Devices, Inc. Sep 2012-Dec 2012  Worked on a discrete GPU to perform functional verification at IP and SOC level. Integrated the C++ test from IP to SOC environment for testing ring oscillator and display module using JTAG/IEEE 1500 standards.  Performed the ATE test pattern generation, scan chain verification, gate level simulations using VCS simulator.  Integrated the testbench environment for the generation of the STIL pattern files .  Resolved the X propagation issues, over shift errors using the Verdi debugging tool.Assistant System Engineer, Tata Consultancy Services Dec 2010-Jul 2011  Worked on a middleware application "Espresso" to support business activities of APPLE Inc.  Designed Library automation System using C++ in UNIX environment with PL/SQL backend design.Technical SkillsEDA Tools : Cadence, Synopsys, Primetime, Verdi, VCS, Liberty NCX, HSpice, SOC Encounter, Tetramax .Software : Xilinx, ModelSim, AWR, Simple Scalar, MATLAB, Perforce, WindRiver Tornado 2.2, MS Office, Visio.Languages : C/C++, Verilog, VHDL, Shell Scripting, PERL, Makefile.OS Platforms :Windows 7/XP, Macintosh, Ubuntu( Linux), Sun Solaris.Relevant CourseworkVLSI Design Advanced VLSI Design Computer ArchitectureTesting and Testable Design Advanced Digital Logic Analog Integrtaed CircuitsDigital Signal Processing Real Time Systems RF and Microwave SystemsAcademic Projects:SRAM Memory Design (IBM 90nm/IBM 130nm)Full Custom : Designed and simulated 768 bits SRAM to obtain optimized area, low power. Characterized 6T SRAMcell for best possible read and write times. Performed the DRC, LVS and HSpice simulations on the full chip.Semi Custom : Performed RTL coding of 2K bit memory, RTL to GDSII flow, custom standard cell library design,parasitic extraction, floor planning using Soc Encounter and static timing analysis (STA) using Prime Time.Error correction code(ECC) Algorithm for a 32 bit word :Designed and implemented the ECC at the schematic levelof the circuit that will enable the correction of any single-bit error. The hamming code algorithm was used with a 6parity bits for a 32 bit word.Digital Circuit Testing :Developed verilog code for various combinational and sequential logic circuits. Carried out thesynthesis and simulation of circuits using Synopsys. Performed ATPG using Tetramax to generate test patterns whichdetects various faults models and fault coverage analysis. scan cell insertion, MBIST,SCAN and March tests.Fine-tuning Cache Hierarchy of an Alpha microprocessor : Computed and optimized CPI for L1 and L2 cache of anAlpha processor for three benchmarks : Go, Anagram and GCC. Defined the cost function for caches in terms ofperformance & area. Determined the best cache configuration by choosing appropriate block size, associativity andreplacement policy of different benchmarks.Design and Implementation of a Train Controller System : Implemented a fixed priority system using deadlinemonotonic algorithm .Designed the schedulability, task parameters and automated control of the traindepending on the sensor(ultra sonic) data.VISA Status : F1.

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