Nagesh Dali Venugopal Contact: +1 630-730-1348
San Jose CA-95110 Email – id:
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Published on: Mar 3, 2016

Transcripts - nageshDV

  • 1. Nagesh Dali Venugopal Contact: +1 630-730-1348 San Jose CA-95110 Email – id: Education MS in Electrical Engineering (DigitalDesign), SanJose StateUniversity, California Fall 2015 Major Course Work: ASIC CMOS Design, DigitalSystem Design & Synthesis and HighSpeed CMOS Circuits, SoC Design & Verification, Advanced DigitalDesign for DSP and Communications, Advanced Computer Architecture BE in Telecommunication engineering, BNMInstituteofTechnology, Bangalore Spring 2012 Course Work: Microprocessor Design, Computer Network, Linear IC Design, C++ OOP’s, Analog Circuits Professional Experience: GlobalEducation and InitiativesStudent Assistant – San Jose State University May (2015) – Present Assist professors to develop proposals, interact with international delegates and update online content of department Assistant Systems Engineer – TATA Consultancy Services Ltd January – July (2013) Developed C++ modules for a telecom client billing system and was a part of the team developing the test plan TechnicalSkills: Key Skills: Constrained Random Verification, Assertions, Coverage, Verilog RTL Design, Simulation and Synthesis, Scripting for regression, StaticTiming Analysis (STA), Version Control, Cache, memory sub-systems, pipelining Design Tools: Synopsys VCS, NC Verilog, Synopsys DesignCompiler HDL/Programming Languages: Verilog, SystemVerilog, C++, Python scripting, UVM Basics Protocols: APB, AHB, PCI, I2C Projects: Automation: Regression Suite November - 2015 Developed a regression suite in Python. Suite verifies the design, generatesandanalyzes the coverage report to update the test bench. It performs regression until a predefined coverageis obtained thereby eliminating constant monitoring and eliminating human effort Verification: Coverage Driven Verification of Atmel-8271 Microcontroller February – 2015 Verified a Timer/counter block using System Verilog assertions, constrained random inputs. Coverage report was generated and analyzed to improve coverage. FPGA: HW/SW Co - Design and HardwareAcceleration on FPGANIOS II Processor March - 2015 Developed a 32 point FFT using C language onan Altera NIOS II processor, improved the performance of the software design by implementing a hardwareaccelerator. Increasein300% performancewas obtained. SoC: Pseudo AHB arbitratordesign usingSystemVerilog May - 2015 Developed AHB like arbitrationscheme for a SoC with 6 master-slaves and 14 slaves using SystemVerilog for design ASIC, CPU: Design and Verification: 8-bit ScalarMicroprocessor October - 2014 Designed a 4 stage pipelined microprocessor, developed a test bench to verify its functionality. Timing analysis was performed for timing closure. Simulation, Synthesis was performed on the design using synopsis VCS, Design Compiler and cadence NC Verilog. Performed Place and Route on the design after synthesis using Cadence Encounter MISC: Other projects include IEEE754 floating point adder implementation, Spread Spectrum Search Engine

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